VLSI Memory Chip Design / Edition 1

by Kiyoo Itoh

Overview

The VLSI memory era truly began when the first production of semiconduc­ tor memory was announced by IBM and Intel in 1970. The announcement had a profound impact on my research at Hitachi Ltd. , and I was forced to change fields: from magnetic thin film to semiconductor memory. This change was so exceptionally sudden and difficult, I feIt like a victim of fate. Looking back, however, I realize how fortunate I was. I have witnessed an unprecedented increase in memory capacity (DRAM, for example, has had a 6-order increase in the last three decades - from the 1-Kb level in 1970 to the 1-Gb level today). I have contributed to this progress with full involvement in memory-chip development over my career. Such rapid progress would have been impossible without many of the inventions and innovative technologies, and without the effort of many talented people. Unfortunately, few systematic books on memory-chip design have been written by experts. Tliis is a result of two factors: the difficulty of involving university professors because of rapidly changing technology requiring huge investments and development resources, and a shortage of time on the part of chip designers in industry due to severe competition in the memory-chip business. Therefore, LSI memory-chip design has been isolated from the outside, preventing a deeper understanding of the technology. This book is based on my 30-year memory-chip (particularly DRAM) design career.

Product Details

ISBN-13:	9783642087363
Publisher:	Springer Berlin Heidelberg
Publication date:	12/15/2010
Series:	Springer Series in Advanced Microelectronics , #5
Edition description:	Softcover reprint of hardcover 1st ed. 2001
Pages:	495
Product dimensions:	6.10(w) x 9.25(h) x 0.04(d)

Read an Excerpt

1. An Introduction to Memory Chip Design

1.1 Introduction

Several essential inventions and innovations, and subsequent sustained efforts [1.1] toward high densities have paved the way to large-scale integrated circuit (LSI) memories, as shown in Fig. 1.1 [1.2]. Since two epoch-making announcements accompanying the start of LSI memory production in 1970 [the first extensive usage of a semiconductor memory chip for the IBM 370 mainframe computers, and the first sales of a 1-Kb dynamic random access memory (DRAM), named the 1103, from Intel, the increase in memory chip capacity has skyrocketed with the help of the ever-higher-density MOS/CMOS design and technology. The resultant LSI memories have given computers, networks, and almost everything with electrical components the benefit of a dramatically reduced cost per bit and far superior performance. Data processors and data terminals, such as personal computers, workstations, and POS terminals, as well as telephone exchanges, digital televisions, and numerical control machines, could not have been produced without them.

The first priority of LSI development is high-density technology. In the past, technology development has been driven by memory because of its inherent features: a strong need for low cost, that is mainly realized by higherdensity technology, and a regular structure of memory chips, that enables easy failure analysis as well as the application of redundancy techniques. Thus, even higher-density technology quickly develops into mass production with an acceptable yield. Fortunately, the vast level of chip production may pay off the tremendous effort involved. Currently, 0.2-µm CMOS technology is being used in the manufacturing of 64-Mb DRAMS, as well as over 400-MHz 32-bit microprocessors, with the numbers of transistors per chip in the 10⁷-10⁸ range. Even below 0.18-µm, CMOS technology has been used in experimental 1-4 Gb DRAMs [1.3] that incorporate over 2-4 billion electrical components, revealing a rapid increase in memory-chip capacity by more than six orders of magnitude (1 Kb-4 Gb) in the past 30 years, since the DRAM advent in 1970. Technologies necessary for 0.1 µm or less are also being investigated and reported at conferences. A typical example of the high-density technology contributing to these advances is fine pattern technology with shorter lightsource wavelengths, as well as the larger wafer and related technology for ever-larger chips. High-density/low-power devices and circuits, such as the one-transistor, one-capacitor memory cell [1.4] and CMOS technology [1.5], are also contributors, as shown in Chap. 2. The resultant reduction in the bit cost of DRAM is shown in Fig. 1.2 [1.7]. Cost has been cut dramatically, at an annual reduction of around 24%, proving of great benefit to system designers. Sometimes, however, excessive competition aiming at a bigger slice of the pie has made the market less profitable for all, with drops in cost, as exemplified by the 256-Kb and 16-Mb generations. The drops has long been experienced as the "silicon cycle", which is fundamentally caused by the relation between supply and demand since the advent of DRAM. Note that the annual bit-cost reduction is around 27%, if the saturated cost of each DRAM generation is assumed to be the same. The difference between the 24% above and 27% implies an ever-increasing chip cost in each successive generation.

SRAM (Static Random Access Memory) using flip-flop memory cells, and non-volatile memories such as ROM (Read-Only Memory) and Flash memory, have advanced with almost the same technology as DRAM. In particular, the invention of non-volatile memories utilizing a floating gate structure is noteworthy [1.6]. Sales of these memory chips have increased annually, as shown in Fig. 1.3 [1.8].

In general, the semiconductor chip is called by the following names, depending on the number of components integrated in the chip: IC (integrated circuit for less than 10³), LSI (large-scale IC for 10³-10⁵), VLSI (verylarge-scale IC for 10⁵-10⁷), ULSI (ultra-large-scale IC for more than 10⁷). Sometimes LSI, VLSI, and ULSI are comprehensively referred to as LSI or VLSI.

In this chapter, the fundamentals of MOS memory-chip technology are described. First, the category of MOS memory chip, the internal organization of the chip, and technology trends in memory chips are discussed. Next, the individual trends of DRAM, SRAM, and non-volatile memory technologies are investigated.

1.2 The Internal Organization of Memory Chips

A memory chip is composed of three blocks [1.9]: a memory cell array, a peripheral circuit, and an input/output (I/O) interface circuit, as shown in Fig. 1.4.

1.2.1 The Meynory Cell Array

A memory cell array comprising a matrix of 2^N rows and 2^M columns can store binary information of 2^N+M bits. For example, if N + M = 20, a memory chip can store 1 Mbit of information, and is called a 1 Mbit (or simply 1 M or 1 Mb) memory chip. Here M denotes 1024 K, with K = 1024. If N + M = 30, we call it a 1 Gbit (1 G or 1 Gb) memory chip, with G = 1024 M. Any cell can be accessed at random with the same speed by selecting both the corresponding row and column. Sometimes, the memory cell array is called memory cell matrix, a memory array, or simply an array. The row is also called the X line or word line, while the column is called the Y line, bit line, or data line. Note that a matrix arrangement minimizes the number of driving circuits of memory cells: the number is (2^N + 2^M), which is a minimum at N = M for the matrix (two-dimensional) arrangement, while it is 2^N+M for a onedimensional arrangement, as shown in Fig. 1.5. For a 1 Mb chip, the matrix arrangement reduces the number from about one million to about two thousand.

1.2.2 The Peripheral Circuit

The block bridges between the memory array and the I/O interface circuit so that they can communicate with each other. It sends write data to a memory cell in the memory array under the control of the interface circuit, or sends read data from the memory cell to the interface circuit. A typical circuit here is a decoder, which is composed of many logic circuits. It selects a logic circuit corresponding to one row or one column, based on a logical set of N or M address signals from address buffers in the interface circuit. Then, a row or column is driven by a driver, which is connected to the output of the logic circuit. Here, an I/O control circuit in the figure controls the transfer of the write or read data in the memory array....

Table of Contents

1. An Introduction to Memory Chip Design.- 2. The Basics of RAM Design and Technology.- 3. DRAM Circuits.- 4. High Signal-to-Noise Ratio DRAM Design and Technology.- 5. On-Chip Voltage Generators.- 6. High-Performance Subsystem Memories.- 7. Low-Power Memory Circuits.- 8. Ultra-Low-Voltage Memory Circuits.- References.