Introduction to Logic Design / Edition 3

by Alan B. Marcovitz

Overview

Introduction to Logic Design by Alan Marcovitz is intended for the first course in logic design, taken by computer science, computer engineering, and electrical engineering students. As with the previous editions, this edition has a clear presentation of fundamentals and an exceptional collection of examples, solved problems and exercises.

The text integrates laboratory experiences, both hardware and computer simulation, while not making them mandatory for following the main flow of the chapters. Design is emphasized throughout, and switching algebra is developed as a tool for analyzing and implementing digital systems. The presentation includes excellent coverage of minimization of combinational circuits, including multiple output ones, using the Karnaugh map and iterated consensus. There are a number of examples of the design of larger systems, both combinational and sequential, using medium scale integrated circuits and programmable logic devices.

The third edition features two chapters on sequential systems. The first chapter covers analysis of sequential systems and the second covers design. Complete coverage of the analysis and design of synchronous sequential systems adds to the comprehensive nature of the text. The derivation of state tables from word problems further emphasizes the practical implementation of the material being presented.

Product Details

ISBN-13:	9780073191645
Publisher:	McGraw Hill LLC
Publication date:	01/09/2009
Edition description:	New Edition
Pages:	656
Product dimensions:	7.50(w) x 9.20(h) x 1.20(d)

Table of Contents

Preface ix

Chapter 1 Introduction 1

1.1 Logic Design 1

1.1.1 The Laboratory 3

1.2 A Brief Review of Number Systems 4

1.2.1 Hexadecimal 8

1.2.2 Binary Addition 9

1.2.3 Signed Numbers 11

1.2.4 Binary Subtraction 14

1.2.5 Binary Coded Decimal (BCD) 16

1.2.6 Other Codes 17

1.3 Solved Problems 19

1.4 Exercises 25

1.5 Chapter 1 Test 27

Chapter 2 Combinational Systems 29

2.1 The Design Process for Combinational Systems 29

2.1.1 Don't Care Conditions 32

2.1.2 The Development of Truth Tables 33

2.2 Switching Algebra 37

2.2.1 Definition of Switching Algebra 38

2.2.2 Basic Properties of Switching Algebra 40

2.2.3 Manipulation of Algebraic Functions 43

2.3 Implementation of Functions with AND, OR, and NOT Gates 48

2.4 The Complement 52

2.5 From the Truth Table to Algebraic Expressions 54

2.6 NAND, NOR, and Exclusive-OR Gates 59

2.7 Simplification of Algebraic Expressions 65

2.8 Manipulation of Algebraic Functions and NAND Gate Implementations 70

2.9 A More General Boolean Algebra 78

2.10 Solved Problems 80

2.11 Exercises 100

2.12 Chapter 2 Test 108

Chapter 3 The Karnaugh Map 111

3.1 Introduction to the Karnaugh Map 111

3.2 Minimum Sum of Product Expressions Using the Karnaugh Map 121

3.3 Don't Cares 135

3.4 Product of Sums 140

3.5 Five- and Six-Variable Maps 143

3.6 Multiple Output Problems 150

3.7 Solved Problems 162

3.8 Exercises 191

3.9 Chapter 3 Test 196

Chapter 4 Function Minimization Algorithms 201

4.1 Quine-McCluskey Method for One Output 201

4.2 Iterated Consensus for One Output 204

4.3 Prime Implicant Tables for One Output 208

4.4 Quine-McCluskey for Multiple Output Problems 216

4.5 IteratedConsensus for Multiple Output Problems 219

4.6 Prime Implicant Tables for Multiple Output Problems 222

4.7 Solved Problems 226

4.8 Exercises 246

4.9 Chapter 4 Test 247

Chapter 5 Designing Combinational Systems 249

5.1 Iterative Systems 250

5.1.1 Delay in Combinational Logic Circuits 250

5.1.2 Adders 252

5.1.3 Subtractors and Adder/Subtractors 256

5.1.4 Comparators 256

5.2 Binary Decoders 258

5.3 Encoders and Priority Encoders 268

5.4 Multiplexers and Demultiplexers 269

5.5 Three-State Gates 274

5.6 Gate Arrays-ROMs, PLAs, and PALs 276

5.6.1 Designing with Read-Only Memories 280

5.6.2 Designing with Programmable Logic Arrays 281

5.6.3 Designing with Programmable Array Logic 284

5.7 Testing and Simulation of Combinational Systems 289

5.7.1 An Introduction to Verilog 289

5.8 Larger Examples 292

5.8.1 A One-Digit Decimal Adder 292

5.8.2 A Driver for a Seven-Segment Display 293

5.8.3 An Error Coding System 301

5.9 Solved Problems 305

5.10 Exercises 348

5.11 Chapter 5 Test 360

Chapter 6 Analysis of Sequential Systems 365

6.1 State Tables and Diagrams 366

6.2 Latches 370

6.3 Flip Flops 371

6.4 Analysis of Sequential Systems 380

6.5 Solved Problems 390

6.6 Exercises 403

6.7 Chapter 6 Test 412

Chapter 7 The Design of Sequential Systems 415

7.1 Flip Flop Design Techniques 420

7.2 The Design of Synchronous Counters 437

7.3 Design of Asynchronous Counters 447

7.4 Derivation of State Tables and State Diagrams 450

7.5 Solved Problems 465

7.6 Exercises 483

7.7 Chapter 7 Test 491

Chapter 8 Solving Larger Sequential Problems 493

8.1 Shift Registers 493

8.2 Counters 499

8.3 Programmable Logic Devices (PLDs) 506

8.4 Design Using ASM Diagrams 511

8.5 One-Hot Encoding 515

8.6 Verilog for Sequential Systems 516

8.7 Design of a Very Simple Computer 518

8.8 Other Complex Examples 520

8.9 Solved Problems 527

8.10 Exercises 537

8.11 Chapter 8 Test 541

Chapter 9 Simplification of Sequential Circuits

View Chapter 9 at mhhe.com/marcovitz

9.1 A Tabular Method for State Reduction 3

9.2 Partitions 10

9.2.1 Properties of Partitions 13

9.2.2 Finding SP Partitions 14

9.3 State Reduction using Partitions 17

9.4 Choosing a State Assignment 22

9.5 Solved Problems 28

9.6 Exercises 44

9.7 Chapter 9 Test 48

Appendix A Relating the Algebra to the Karnaugh Map 543

Appendix B Answers to Selected Exercises 548

Appendix C Chapter Test Answers 573

Appendix D Laboratory Experiments 587

D.1 Hardware Logic Lab 587

D.2 WinBreadboardTM and MacBreadboardTM 591

D.3 Introduction to LogicWorks 593

D.4 A Set of Logic Design Experiments 598

D.4.1 Experiments Based on Chapter 2 Material 598

D.4.2 Experiments Based on Chapter 5 Material 600

D.4.3 Experiments Based on Chapter 6 Material 603

D.4.4 Experiments Based on Chapter 7 Material 605

D.4.5 Experiments Based on Chapter 8 Material 606

D.5 Layout of Chips Referenced in the Text and Experiments 607

Appendix E Complete Examples 612

Index 629